1. Field of the Invention
This invention relates to transistors, and particularly to field effect silicon-on-insulator transistors.
2. General Description of the Prior Art
Field effect transistors may be constructed of insulating substrates, and their use could be extended by modifications which would increase their switching speeds, while at the same time preserving their present low power requirements, that is, achieving a lower speed-power product than is currently obtainable. One factor limiting such improvement is that of channel length and the distance across the gate region of a transistor between the source and drain. Any reduction in this spacing in a conventional transistor of this type on an insulating substrate would result in a source-drain short at the semi-conductor substrate interface where this channel length is shortest due to the physical properties of this interface. Such a short would prevent other proper operation of the device, and, of course, must be avoided.
A second problem is that of gate-channel capacitance which must be minimized if frequency response is to be extended. To insure proper operation of such a transistor, the gate electrode must just overlap the source and drain regions slightly. Presently, the minimum overlap (which ideally should be made shorter) is limited by tolerances required by present-day techniques of wafer-mask alignment. This tolerance must be such as to insure that a control channel is formed by the gate electrode over the entire distance between the source and drain regions of the device. Otherwise, part of the gate region would not be under gate control, and a permanent diode would result, preventing operation of the device.
In order to reduce gate-channel capacitance, a field effect transistor has been developed in which a polycrystalline silicon P+ gate electrode is positioned over a conventional P type gate region, the latter separating the N+ source and drain regions. It has the advantage of virtually no gate overlap over source or drain, as the silicon gate is used to define N+ diffusion regions into the wafer making up the source and drain. Although this self-alignment technique does away with gate overlap capacitance, it does nothing to decrease channel length, i.e., source to drain spacing, one of the limitations referred to above.
Another means of reducing gate overlap capacitance is incorporated in another form of field effect transistor by means of an ion implantation technique as follows. N+ source and drain regions and a P type gate region are defined in a normal manner at a convenient spacing. Next, a gate electrode is made as small as possible, centered over the gate P region, and it defines an area smaller than the gate region, being limited by the ability to define a metal electrode. Next, the entire device is bombarded with N ions, causing source and drain N+ regions to extend into sides of the originally doped P region to thus effectively extend the source and drain gate regions up to a sharp line by the shadow of the gate electrode. This thus quite effectively prevents a gate electrode overlap over the source and drain regions and does away with the gate overlap capacitance. One disadvantage of this geometry is that because of the sharp doping profile achieved by the described technique, there may result a low voltage breakdown of the device due to high electric field intensities between the gate and source and drain regions.
Still another device, referred to as a double diffused metal oxide semi-conductor device, has been proposed as an improved higher speed field effect transistor. It, too, uses an auxiliary gate region, but differs from the self-alignment device described above in that the centrally positioned gate region is doped N rather than P, except for a very narrow region adjacent to the drain diffusion, which is doped P. It would seem that this geometry could provide a higher speed device. However, it also appears that there may be a significant signal propagation delay across the source to drain channel as a result of gate influence on the entire channel area, making the entire channel area a surface effect area. This, of course, could reduce or significantly limit any increase in switching speeds.